The fabrication of semiconductor devices such as integrated circuits, memory cells, and the like, involve a series of manufacturing operations that are performed to define features on semiconductor wafers (“wafers”). The wafers include integrated circuit devices in the form of multi-level structures defined on a silicon substrate. At a substrate level, transistor devices with diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define a desired integrated circuit device. Also, patterned conductive layers are insulated from other conductive layers by dielectric materials.
To build an integrated circuit, transistors are first created on the surface of the wafer. The wiring and insulating structures are then added as multiple thin-film layers through a series of manufacturing process steps. Typically, a first layer of dielectric (insulating) material is deposited on top of the formed transistors. Subsequent layers of metal (e.g., copper, aluminum, etc.) are formed on top of this base layer, etched to create the conductive lines that carry the electricity, and then filled with dielectric material to create the necessary insulators between the lines. The process used for producing copper lines is referred to as a dual Damascene process, where trenches are formed in a planar conformal dielectric layer, vias are formed in the trenches to open a contact to the underlying metal layer previously formed, and copper is deposited everywhere. Copper is then planarized (overburden removed), leaving copper in the vias and trenches only.
When copper materials are used metal barrier layers are need to prevent the copper from diffusing into the interlayer dielectric (ILD) layer. The diffusion of the copper into the ILD is sometimes referred to as poisoning of the ILD. The material for the metal barriers forms excellent barriers to copper diffusion. In addition, the manufacturers of semiconductor devices are investigating materials for use as capping layers to prevent the oxidation of layers disposed below the capping layers.
It is within this context that the embodiments arise.